1. Field of the Invention
The present invention relates to a data processing circuit and a data processing method.
2. Description of the Related Art
FIG. 10 illustrates the configuration of a data input processing system 1 that is applied to car audio systems or the like. The data input processing system 1 includes a main device 10 and a display device 20 that is detachable from the main device 10.
The main device 10 is equipped with mechanisms and circuits to achieve the functions of a car audio system such as a CD or DVD player, a radio receiver, etc. On the other hand, the display device 20 is provided with a display panel 21 to indicate information on the control or the operation of the car audio system, a data input processing circuit 22, a key scanning circuit 23, a rotary encoder 24, and a remote control receiver 25.
The main device 10 is equipped with a controller 11 to control indication on the display panel 21, and to receive signals from the key scanning circuit 23, the rotary encoder 24, and the remote control receiver 25. The controller 11 inputs a clock signal CL, a data input signal DI, and a chip enable signal CE to an input interface 221 in the display device 20 for the display control or for the reception of the signals.
The input processing circuit 22 in the display device 20 includes the input interface 221 that communicates with the controller 11, a control register 222 that memorizes input data that is input from the controller 11, a display control unit 223 that controls the display panel 21 based on display data that is input as the input data, a signal generating unit 224 that provides a driving signal such as an operational clock signal for the display control unit 223, and a signal selecting circuit 225 that selects either a key scanning signal or a rotary encoder detecting signal (hereinafter, these are collectively referred to as a slow processing signal), corresponding to the address data that is input from the controller 11 as a data-output request to be memorized at the control register 222, and that outputs the selected slow processing signal.
The display device 20 is also equipped with a circuit (e.g., remote control receiver 25) that generates a signal with a short sampling period (hereinafter, referred to as a fast processing signal). The fast processing signal cannot be synchronized with a clock signal that is input from the main device 10 due to the insufficient processing capacity of a processor mounted on the display device 20, and therefore, it is output to the main device 10 via an independent signal line different from a signal line for the slow processing signals. (refer to Japanese Patent Application Laid-Open Publication No. 8-221174)
In the case, as above, that individual signal lines to output a fast processing signal and a slow processing signal are arranged independently, the number of lines to connect the main device 10 and the display device 20 increased, and thus wiring becomes complicated. Thereby, the possibility of such a trouble as a faulty connection increases, and the manufacturing cost also increases due to the increased number of parts.